Non-volatile semiconductor memory devices are advantageous in that the information stored therein is not lost when the power supply is removed. A description of a typical non-volatile MOS ROM wherein the stored information is permanently fixed upon manufacture by the gate level mask or moat mask is described in U.S. Pat. No. 3,541,543, assigned to the present assignee. In addition, various electrically programmable ROM (EPROM) devices have heretofore been developed such as described in U.S. Pat. No. 3,984,822, which employs a floating gate in a double level polysilicon MOS ROM. In this device, a floating gate is provided which may be charged by injection of electrons from the channel and the device stays charged for years. Electrically alterable ROMs (EEPROMs) have also been developed which use floating gate cells with dual injection (both holes and electrons) so that the gates may be charged or discharged, such as described in U.S. Pat. Nos. 3,881,180 and 3,882,469, assigned to the present assignee.
Floating gate MOS memory cells have been heretofore developed which are fabricated by an n channel, silicon-gate, self-aligned, double level polysilicon process which is compatible with standard processing techniques. In these processes, implants of buried n+ material are patterned and selective oxidation is used to grow a thin oxide layer over the channel areas and a relatively thick oxide over the n+ diffusion areas. This process and the resulting memory device is described in U.S. Pat. No. 4,151,021, assigned to the present assignee.
While such prior memory devices have worked well in practice, the prior devices have resulted in relatively deep effective n+ junctions and have not thus been completely satisfactory with respect to punch-through characteristics. A need has thus arisen for a read only memory device with shallower effective junctions but with effective channel isolation. Moreover, previously developed non-volatile memory devices have had reduced effective electrical channel lengths due to lateral migration of the differentially grown oxide. It is thus desirable to develop non-volatile memories with increased effective electrical channel length. Further, in previously developed non-volatile devices, the sheet resistance of the formed column lines has often been excessively high, and a need has arisen for a technique for fabricating non-volatile memories to enable reduction of the sheet resistance of the column lines.